1. Field of the Invention
The present invention relates to an integration circuit (IC) process, and more specifically, to a mixed mode process for IC manufacturing.
2. Description of the Prior Art
A metal-oxide semiconductor (MOS) transistor is a common electrical device used in integrated circuits. The MOS transistor is a unit, having four nodes, formed by a gate, a source and a drain. By utilizing channel effects generated by the gate of the MOS under different gate voltages, the MOS is often made to function as a digitalized solid switch applied on various integrated circuits of memory or logic devices.
Please refer to FIG. 1 of a perspective view of a MOS transistor 12 according to the prior art. As shown in FIG. 1, the MOS transistor 12 is formed on a substrate 10 and comprises a gate oxide layer 14, a gate 16 formed atop the gate oxide layer 14, a spacer 18 formed on either sides of the gate 16 and two doped areas, employed as a source 20 and a drain 22 of the MOS transistor 12, formed in portions of the substrate 10 adjacent to either sides of the MOS transistor 12. Normally, a self-aligned silicide (salicide) process is performed to form a silicide layer 26 on surfaces of the source 20 and the drain 22. In order to prevent the silicide layer 26 from being formed on a top surface of the gate 16 during the salicide process, a cap layer 24, comprising silicon oxide, is formed on the top surface of the gate 16 before the salicide layer 26 is formed.
In addition to the MOS transistor, a capacitor is also a frequently applied device in semiconductor circuits. In semiconductor processing, a capacitor on a semiconductor wafer is designed with a bottom electrode plate and a top electrode plate electrically isolated by a dielectric layer between the bottom and top electrode plates at a predetermined distance. When a voltage is applied to the two electrode plates, charge is stored between them. The capacitance of the capacitor varies due to the amount of stored charge, which is directly related to the surface area of the two electrode plates and the dielectric constant of the dielectric layer, as well as to the material used for the dielectric layer.
Please refer to FIG. 2 of the perspective view of a capacitor 28 according to the prior art. As shown in FIG. 2, a silicon substrate 30 comprises a field oxide layer 32 formed on a surface of the silicon substrate 30. The capacitor 28 is formed on a silicon substrate 30 and comprises a first polysilicon layer 34 formed within a predetermined area on a surface of the field oxide layer 32, a dielectric layer 36 formed on the first polysilicon layer 34 and a second polysilicon layer formed within a predetermined area on a top surface of the dielectric layer 36. Wherein the first and second polysilicon layers 34 and 38 are respectively employed as a bottom electrode plate and a top electrode plate of the capacitor 28, and the dielectric layer 36 is employed as a capacitor dielectric layer of the capacitor 28.
However, the line width in semiconductor manufacturing decreases as technology progresses. It has become an important issue in semiconductor manufacturing to improve the production efficiency by producing the MOS transistor 12 and the capacitor 28 with excellent performance on a wafer with less possible surface area. A new IC manufacturing process is therefore a must.
It is therefore a primary object of the present invention to provide a mixed mode process for integration circuits (IC) to improve the manufacturing efficiency during the production of devices with highly integrated circuits.
According to the claimed invention, a semiconductor substrate has a surface comprises at least a conductive region, a metal-oxide-semiconductor (MOS) transistor region and a capacitor region. Portions of the surface of the semiconductor substrate further comprise a field oxide. The mixed mode process begins with sequentially forming a gate oxide layer, a first polysilicon layer, a polycide layer and a first inter-polysilicon oxide (IPO) layer on the semiconductor substrate. A first photo-etching-process (PEP) is then performed to remove portions of the first IPO layer, polycide layer and the first polysilicon layer to simultaneously form a first stacked structure and a second stacked structure respectively in the MOS transistor region and the capacitor region. A second IPO layer and a second polysilicon layer are sequentially formed on the semiconductor substrate thereafter to cover the first and second stacked structures, and a second PEP is performed to remove portions of the second polysilicon layer to simultaneously form a conductive wire and a top electrode plate of a capacitor respectively in the conductive region and on the second stacked structure. A dielectric layer is then formed on the semiconductor substrate to cover the conductive wire, the first stacked structure, the top electrode plate and the second stacked structure. By performing an etching process to remove portions of the dielectrice layer and the second IPO layer, a spacer is formed on either sides of the conductive wire, the top electrode plate and the second stacked structure. Finally, a self-aligned silicide (salicide) process is performed to form a silicide layer respectively on the conductive wire, top electrode plate and portions of the surface of the semiconductor substrate adjacent to either side of the first stacked structure in the MOS transistor region.
It is an advantage of the present invention against the prior art that the conductive wire, the MOS transistor and the capacitor are simultaneously formed on the silicon substrate with the least number of steps to improve the production efficiency without influencing the performance of the wire, the MOS transistor and the capacitor. In addition, the first and second IPO layers, employed as a capacitor dielectric layer of the capacitor in the present invention, have a same composition. The stability of the capacitance of the capacitor is therefore assured. Besides, the salicide layer formed on the top electrode plate can significantly reduce the resistance of the top electrode plate to increase the product life of the capacitor. Consequently, the mixed mode process revealed in the present invention can be applied in the production for device with highly integrated circuits to achieve a strong competitiveness of the product.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the multiple figures and drawings.